Gates & Circuits
Circuit Depth
The number of sequential time-steps required to execute a quantum circuit, a key factor in how much error accumulates.
Definition
Circuit depth measures the longest sequential chain of gate operations in a quantum circuit, from input to output — distinct from the total number of gates, since gates acting on different qubits at the same time don't add to depth. Deeper circuits take longer to run and accumulate more error.
In depth
Circuit depth is the number of layers of gates in a quantum circuit when gates that act on different qubits are run at the same time. It is the length of the longest chain of operations that must happen one after another, and so it sets the minimum run time. Depth differs from gate count: a circuit with a thousand gates can have a depth of ten if they can all be parallelized, and a depth of a thousand if they cannot. Two-qubit depth, counting only entangling gates, is often the figure that matters most, since those gates are the slowest and noisiest.
Depth matters because noise accumulates. Each layer takes time during which qubits decohere, and each gate adds error. A device with a two-qubit error of 0.5 percent can run roughly a few hundred entangling layers before the output is mostly noise. IBM's 2023 utility experiment on 127 qubits used circuits with about 60 layers and 2,880 two-qubit gates and needed error mitigation to extract an answer. Algorithms are therefore judged by depth: variational circuits aim for tens of layers, and fault-tolerant algorithms such as Shor's need depths of billions, which only error correction can support.
Reducing depth is a central part of compilation. Techniques include parallelizing independent gates, choosing layouts that reduce SWAPs, using native gates, and rewriting circuits into shorter equivalents. Different algorithms scale differently: the quantum Fourier transform on n qubits has depth of order n squared when written naively and of order n log n when approximated, and Grover's algorithm needs about the square root of N iterations of an oracle. Other measures include T-depth, which counts layers of the expensive T gates in fault-tolerant machines.
Technical Definition
Because decoherence and gate errors compound with each additional time step, circuit depth is often a more critical practical constraint on NISQ hardware than total qubit count or total gate count alone.
Visual Explanation: An Analogy
Think of circuit depth like the number of sequential steps in a recipe that must happen one after another (you can't frost a cake before it's baked), as opposed to steps that could happen simultaneously (chopping vegetables while the oven preheats).
Key facts
| Item | Detail |
|---|---|
| Definition | Length of the longest sequence of gates that cannot be parallelized |
| Versus gate count | Gate count is the total, and depth is the sequential length |
| IBM 2023 utility experiment | 127 qubits, about 60 layers, 2,880 two-qubit gates |
| Related measures | Two-qubit depth, T-depth, and width |
| Practical limit | A few hundred entangling layers on noisy devices |
Where the idea comes from
Depth as a measure of parallel complexity comes from classical circuit theory. It became a practical constraint for quantum computers in the 2010s as researchers on noisy devices tried to fit algorithms into short coherence windows.
Real-World Use Cases
- A key constraint motivating NISQ-era algorithm design (like VQE and QAOA) to use shallow circuits
- Directly relevant to why hardware-aware circuit compilation, discussed in our Research Papers, matters so much for practical performance
How it differs from related ideas
- Depth measures time, and width measures the number of qubits.
- A shallow circuit with many gates is less affected by decoherence than a deep circuit with few gates.
- T-depth counts only layers containing T gates, which dominate cost in fault-tolerant machines.
Frequently asked questions
What is circuit depth?
The number of sequential layers of gates in a quantum circuit, which determines how long it takes to run and how much noise builds up.
Why does depth limit what hardware can do?
Because each layer takes time and adds error, so deep circuits exceed the coherence time or error budget of noisy devices.
How can depth be reduced?
By parallelizing gates, using native gates, optimizing the qubit layout, and rewriting the circuit with equivalent shorter sequences.
Related Terms
Keep exploring
- Algorithm: Quantum Approximate Optimization Algorithm (QAOA)
- Algorithm: Quantum Fourier Transform (QFT)
- Hardware: IBM Heron (r1, r2, and r3)
- Hardware: IBM Eagle